This invention relates to method and means for testing the storage cells of a static semiconductor memory, and more particularly to improvements therein.
It is customary, in testing static semiconductor memories, to write test patterns and then to read out these test patterns. It has been found that when data is written into the memory and read out immediately thereafter, although the memory passes that test, if an interval of anywhere from 10 to 30 seconds is allowed to elapse before the data is read out again, the memory data will have changed in certain of its storage cells. These are called "delay fails." These delay fails are caused by the load devices used in the memory cell being defective and the reason that this is undetected when an active test such as has been described is conducted is that there is a stray capacitance which exists between the node into which the load device is connected in the memory cell and the substrate, which, over short intervals such as have been indicated, acts to maintain the voltage which would otherwise be supplied to the storage cell through the load device. The stray capacitance is eventually discharged by shunt leakage current.
Since there is always stray capacitance present as a result of the cell construction, unless the effects thereof can be counteracted or minimized, the testing of cells has to proceed at a rather slow pace in order to accurately detect the delay fails which are costly in terms of labor and test throughput.